DC & Switching Characteristics
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
75
ps
fSS
Spread spectrum modulation
frequency
30
150
0.6
kHz
%
% spread
tARESET
Percentage spread for spread
spectrum frequency (10)
0.4
10
0.5
ns
Minimum pulse width on areset
signal
tARESET_RECON Minimum pulse width on the
500
ns
FIG
aresetsignal when using PLL
reconfiguration. Reset the PLL after
scandataoutgoes high.
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades (Part 1 of 2)
Symbol
Parameter
Min Typ
Max
Unit
fIN
Input clock frequency
3
650
MHz
(1), (2)
fINPFD
Input frequency to PFD
Input clock duty cycle
3
420
60
MHz
%
fINDUTY
fEINDUTY
40
40
External feedback clock input duty
cycle
60
%
tINJITTER
tEINJITTER
tFCOMP
Input clock period jitter
200 (3)
200 (3)
6
ps
ps
ns
External feedback clock period jitter
Externalfeedbackclock compensation
time (4)
fOUT
Output frequency for internal global or
regional clock
0.3
450
MHz
fOUT_EXT
tOUTDUTY
Output frequency for external clock (3) 0.3
500
55
MHz
%
Duty cycle for external clock output
45
(when set to 50%)
tJITTER
Period jitter for external clock output
(6)
100 ps for >200-MHz outclk
20 mUI for <200-MHz outclk
ps or
mUI
tCONFIG5,6
Time required to reconfigure the scan
chains for PLLs 5 and 6
289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the scan
chains for PLLs 11 and 12
193/fSCANCLK
Altera Corporation
January 2006
4–95
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
