PLL Specifications
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 2 of 3)
Symbol
tEINJITTER
tFCOMP
Parameter
Min Typ
Max
200 (3)
6
Unit
ps
External feedback clock period jitter
External feedback clock
ns
compensation time (4)
fOUT
Output frequency for internal global
or regional clock
0.3
0.3
45
357
369
55
MHz
MHz
%
fOUT_EXT
tOUTDUTY
tJITTER
Output frequency for external clock
(3)
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
100 ps for >200-MHz outclk
20 mUI for <200-MHz outclk
ps or
mUI
tCONFIG5,6
tCONFIG11,12
Time required to reconfigure the
scan chains for PLLs 5 and 6
289/fSCANCLK
Time required to reconfigure the
scan chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (5)
22
MHz
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
(7) (11)
(9)
100
μs
tLOCK
fVCO
Time required to lock from end of
device configuration (11)
10
400
μs
PLL internal VCO operating range
300
600 (8)
MHz
4–98
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
