DC & Switching Characteristics
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
tOUTDUTY
Duty cycle for external clock output
45
55
%
(when set to 50%)
tJITTER
Period jitter for external clock output
(6)
100 ps for >200-MHz outclk
20 mUI for <200-MHz outclk
ps or
mUI
tCONFIG5,6
Time required to reconfigure the
scan chains for PLLs 5 and 6
289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the
scan chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (5)
22
MHz
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays) (7)
(11)
(9)
100
μs
tLOCK
Time required to lock from end of
10
400
μs
device configuration (11)
fVCO
PLL internal VCO operating range
300
600 (8)
MHz
ps
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
50
75
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
ps
fSS
Spread spectrum modulation
frequency
30
0.5
10
150
0.6
kHz
%
% spread
tARESET
Percentage spread for spread
spectrum frequency (10)
ns
Minimum pulse width on areset
signal
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3)
Symbol
Parameter
Min Typ
Max
Unit
fIN
Input clock frequency
3
480
MHz
(1), (2)
fINPFD
Input frequency to PFD
Input clock duty cycle
3
420
60
MHz
%
fINDUTY
fEINDUTY
40
40
External feedback clock input duty
cycle
60
%
tINJITTER
Input clock period jitter
200 (3)
ps
Altera Corporation
January 2006
4–97
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
