Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
Typ Max
-8 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
Min
Typ
Max
Min
fHSCLK (Clock
frequency)
(LVDS,LVPECL,
HyperTransport
technology)
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
10
156
231
312
311
624
624
624
624
624
462
311
10
115.5
231
231
270
462
462
462
462
462
462
270
10
115.5
231
231
270
462
462
462
462
462
462
270
MHz
MHz
50
50
50
150
100
300
300
300
300
300
100
100
150
100
300
300
300
300
300
100
100
150
100
300
300
300
300
300
100
100
MHz
MHz
f
HSCLK = fHSDR / W
MHz
fHSDR Device operation, J = 10
(LVDS,LVPECL,
HyperTransport
technology)
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
J = 8
J = 7
J = 4
J = 2
J = 1 (LVDS and LVPECL
only)
fHSCLK (Clock
frequency)
(PCML)
W = 4 to 30 (Serdes used)
10
77.75
150
155.5
200
311
311
311
311
311
300
200
400
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
W = 2 (Serdes bypass)
50
50
77.5
155
50
77.5
155
W = 2 (Serdes used)
150
100
300
300
300
300
300
100
100
f
HSCLK = fHSDR / W
W = 1 (Serdes bypass)
100
100
W = 1 (Serdes used)
Device operation,
fHSDR
(PCML)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1
All
100
100
155
155
400
100
100
155
155
400
TCCS
ALTERA [ ALTERA CORPORATION ]
