PLL Specifications
Tables 4–127 through 4–129 describe the Stratix device enhanced PLL
specifications.
PLL
Specifications
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)
Symbol
Parameter
Min Typ
Max
Unit
fIN
Input clock frequency
3
684
MHz
(1), (2)
fINPFD
Input frequency to PFD
Input clock duty cycle
3
420
60
MHz
%
fINDUTY
fEINDUTY
40
40
External feedback clock input duty
cycle
60
%
tINJITTER
tEINJITTER
tFCOMP
Input clock period jitter
200 (3)
200 (3)
6
ps
ps
ns
External feedback clock period jitter
External feedback clock
compensation time (4)
fOUT
Output frequency for internal global
or regional clock
0.3
0.3
45
500
526
55
MHz
MHz
%
fOUT_EXT
tOUTDUTY
tJITTER
Output frequency for external clock
(3)
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
100 ps for >200-MHz outclk
20 mUI for <200-MHz outclk
ps or
mUI
tCONFIG5,6
tCONFIG11,12
Time required to reconfigure the
scan chains for PLLs 5 and 6
289/fSCANCLK
Time required to reconfigure the
scan chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (5)
22
MHz
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
100
μs
counters/delays) (7)
tLOCK
Time required to lock from end of
device configuration
10
400
μs
fVCO
PLL internal VCO operating range
300
50
800 (8)
MHz
ps
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
4–94
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
