PLL Specifications
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades (Part 2 of 2)
Symbol
tSCANCLK
tDLOCK
Parameter
Min Typ
Max
22
Unit
MHz
μs
scanclkfrequency (5)
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays) (7)
(11)
(9)
100
tLOCK
Time required to lock from end of
10
400
μs
device configuration (11)
fVCO
PLL internal VCO operating range
300
50
800 (8)
MHz
ps
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
75
ps
fSS
Spread spectrum modulation
frequency
30
150
0.6
kHz
%
% spread
tARESET
Percentage spread for spread
spectrum frequency (10)
0.4
10
0.5
ns
Minimum pulse width on areset
signal
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency
3
565
MHz
(1), (2)
fINPFD
Input frequency to PFD
Input clock duty cycle
3
420
60
MHz
%
fINDUTY
fEINDUTY
40
40
External feedback clock input duty
cycle
60
%
tINJITTER
tEINJITTER
tFCOMP
Input clock period jitter
200 (3)
200 (3)
6
ps
ps
ns
External feedback clock period jitter
External feedback clock
compensation time (4)
fOUT
Output frequency for internal global
or regional clock
0.3
0.3
420
434
MHz
MHz
fOUT_EXT
Output frequency for external clock
(3)
4–96
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
