PLLs and Clock Networks
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–17 shows the PLLs available for
each Arria GX device and their type.
Table 2–17. Arria GX Device PLL Availability Notes (1), (2)
Fast PLLs
Enhanced PLLs
Device
1
2
3 (3) 4 (3)
7
8
9 (3)
10 (3)
5
6
11
12
EP1AGX20
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP1AGX35
EP1AGX50 (4)
EP1AGX60(5)
EP1AGX90
v
v
v
v
v
v
v
v
v
v
v
v
Notes to Table 2–17:
(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must
drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast
PLL.
(2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but
the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this
table.
(3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
(4) 4 or 8 PLLs are available depending on C or D device and the package option.
(5) 4or 8 PLLs are available depending on C, D, or E device option.
2–88
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
