Arria GX Architecture
Arria GX clock networks can be disabled (powered down) by both static
and dynamic approaches. When a clock net is powered down, all the logic
fed by the clock net is in an off-state thereby reducing the overall power
consumption of the device. Global and regional clock networks can be
powered down statically through a setting in the configuration file (SOF
or POF). Clock networks that are not used are automatically powered
down through configuration bit settings in the configuration file
generated by the Quartus II software. The dynamic clock enable or
disable feature allows the internal logic to control power up/down
synchronously on GCLKand RCLKnets and PLL_OUTpins. This function
is independent of the PLL and is applied directly on the clock network or
PLL_OUTpin, as shown in Figures 2–58 through 2–60.
Enhanced and Fast PLLs
Arria GX devices provide robust clock management and synthesis using
up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
clocking, reconfigurable bandwidth, phase control, and reconfigurable
phase shifting, the Arria GX device’s enhanced PLLs provide you with
complete control of your clocks and system timing. The fast PLLs provide
general purpose clocking with multiplication and phase shifting as well
as high-speed outputs for high-speed differential I/O support. Enhanced
and fast PLLs work together with the Aria GX high-speed I/O and
advanced clock architecture to provide significant improvements in
system performance and bandwidth.
Altera Corporation
May 2008
2–87
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
