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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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PLLs and Clock Networks  
Figure 2–61 shows a top-level diagram of the Arria GX device and PLL  
floorplan.  
Figure 2–61. PLL Locations  
CLK[15..12]  
11  
5
7
FPLL7CLK  
1
2
CLK[3..0]  
PLLs  
FPLL8CLK  
8
12  
6
CLK[7..4]  
Figures 2–62 and 2–63 shows global and regional clocking from the fast  
PLL outputs and side clock pins. The connections to the global and  
regional clocks from the fast PLL outputs, internal drivers, and CLKpins  
on the left side of the device are shown in Table 2–19.  
2–90  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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