PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs Note (1)
RCLK1
RCLK3
RCLK2
RCLK0
C0
C1
C2
C3
Fast
PLL 7
C0
C1
C2
C3
Fast
PLL 8
RCLK4
RCLK6
RCLK7
GCLK0
GCLK1
GCLK2
GCLK3
RCLK5
Note to Figure 2–63:
(1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 1 of 3)
Left Side Global & Regional Clock
Network Connectivity
Clock Pins
CLK0p
v
v
v
v
v
v
CLK1p
CLK2p
CLK3p
v
v
v
v
v
v
v
v
v
v
Drivers from Internal Logic
2–92
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
