PLLs and Clock Networks
Figure 2–57. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Regional Clock Network [7..0]
Clock [23..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
■
Figures 2–58 through 2–60 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
2–84
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
