Arria GX Architecture
Figure 2–58. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
2
2
CLKn
Pin
Internal
Logic
CLKSELECT[1..0]
2
(1)
Static Clock Select (2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–58:
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
Figure 2–59. Regional Clock Control Blocks
CLKp
Pin
CLKn
Pin
(2)
PLL Counter
Outputs
2
Internal
Logic
Static Clock Select
(1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–59:
(1) These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically
controlled during user mode operation.
(2) Only the CLKnpins on the top and bottom of the device feed to regional clock select.
Altera Corporation
May 2008
2–85
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
