Arria GX Architecture
Figure 2–56. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
Clock Pins or PLL Clock
Outputs Can Drive
CLK[15..12]
CLK[15..12]
Dual-Regional Network
CLK[3..0]
CLK[3..0]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form buses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–57).
Altera Corporation
May 2008
2–83
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
