PLLs and Clock Networks
Figure 2–55. Regional Clocks
CLK[15..12]
11 5
7
RCLK
RCLK
[31..28]
[27..24]
Arria GX
Transceiver
Block
RCLK
[3..0]
RCLK
[23..20]
1
CLK[3..0]
2
RCLK
[7..4]
RCLK
[19..16]
Arria GX
Transceiver
Block
RCLK
[11..8]
RCLK
[15..12]
8
12 6
CLK[7..4]
Dual-Regional Clock Network
A single source (CLKpin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant), which allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–56. Corner PLLs cannot drive dual-regional clocks.
2–82
Altera Corporation
Arria GX Device Handbook, Volume 1
May 2008
ALTERA [ ALTERA CORPORATION ]
