Arria GX Architecture
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–54 shows the 12 dedicated CLK
pins driving global clock networks.
Figure 2–54. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Arria GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0]input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLKpins
symmetrically drive the RCLKnetworks in a particular quadrant, as
shown in Figure 2–55.
Altera Corporation
May 2008
2–81
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
