Arria GX Architecture
f
For more information about DSP blocks, refer to the DSP Blocks in Arria
GX Devices chapter in volume 2 of the Arria GX Device Handbook.
Table 2–15. DSP Block Signal Sources and Destinations
LAB Row at
Interface
Control Signals Generated
Data Inputs Data Outputs
0
clock0
aclr0
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
ena0
mult01_saturate
addnsub1_round/
accum_round
addnsub1
signa
sourcea
sourceb
1
clock1
aclr1
A2[17..0]
B2[17..0]
OC[17..0]
OD[17..0]
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
2
clock2
aclr2
A3[17..0]
B3[17..0]
OE[17..0]
OF[17..0]
ena2
mult23_saturate
addnsub3_round/
accum_round
addnsub3
sign_b
sourcea
sourceb
3
clock3
aclr3
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
Altera Corporation
May 2008
2–79
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
