Digital Signal Processing Block
Figure 2–53. DSP Block Interface to Interconnect
Direct Link Interconnect
from Adjacent LAB
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
C4 Interconnect
R4 Interconnect
36
DSP Block
Row Structure
LAB
36
16
LAB
18
16
12
36
Control
36
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
Row Interface
Block
DSP Block to
36 Inputs per Row
36 Outputs per Row
LAB Row Interface
Block Interconnect Region
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in Table 2–15.
2–78
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
