Arria GX Architecture
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (refer to “PLLs and Clock Networks” on
page 2–80).
Figure 2–70 illustrates the signal paths through the I/O block.
Figure 2–70. Signal Path Through the I/O Block
Row or Column
io_clk[7..0]
To Other
IOEs
io_dataina
io_datainb
To Logic
Array
oe
ce_in
io_oe
io_ce_in
io_ce_out
io_aclr
ce_out
Control
Signal
Selection
IOE
aclr/apreset
sclr/spreset
From Logic
Array
clk_in
io_sclr
io_clk
clk_out
io_dataouta
io_dataoutb
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out. Figure 2–71 illustrates the control signal
selection.
Altera Corporation
May 2008
2–105
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
