Arria GX Architecture
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
Delay
t
CO
ce_out
V
CCIO
PCI Clamp (2)
V
CCIO
Programmable
Pull-Up
aclr/apreset
Resistor
Chip-Wide Reset
On-Chip
Termination
Output Register
Output
Pin Delay
D
Q
Drive Strength Control
Open-Drain Output
sclr/spreset
ENA
CLRN/PRN
Input Pin to
Logic Array Delay
Bus-Hold
Circuit
Input Pin to
Input Register Delay
Input Register
clkin
D
Q
ce_in
ENA
CLRN/PRN
Notes to Figure 2–72:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
The Arria GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Altera Corporation
May 2008
2–107
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
