I/O Structure
Figure 2–66. Arria GX Device Fast PLL
Post-Scale
Counters
VCO Phase Selection
Selectable at each PLL
Output Port
Clock
Switchover
Circuitry (4)
Phase
Frequency
Detector
diffioclk0 (2)
load_en0 (3)
Global or
regional clock (1)
÷c0
÷c1
÷c2
8
Charge
Pump
(3)
load_en1
Loop
Filter
÷k
÷n
PFD
VCO
4
Clock
Input
diffioclk1 (2)
4
8
Global clocks
4
Global or
regional clock (1)
Regional clocks
to DPA block
÷c3
÷m
8
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–66:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)
circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support
mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Arria GX fast PLLs only support manual clock switchover.
f
For more information about enhanced and fast PLLs, refer to the PLLs in
Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook.
Refer to “High-Speed Differential I/O with DPA Support” on page 2–124
for more information about high-speed differential I/O support.
The Arria GX IOEs provide many features, including:
I/O Structure
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Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip termination for differential standards
Programmable pull-up during configuration
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
2–100
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
