Arria GX Architecture
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 2 of 2)
Top Side Global and
Regional Clock Network
Connectivity
c2
v
v
v
v
v
v
v
v
v
v
v
v
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 11 outputs
c0
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs (Part 1 of 2)
Bottom Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK4p
v
v
v
v
v
v
v
v
v
v
v
v
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
v
GCLKDRV1
Altera Corporation
May 2008
2–97
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
