PLLs and Clock Networks
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs
(Part 2 of 2)
Bottom Side Global and
Regional Clock Network
Connectivity
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 6 outputs
c0
v
v
v
v
v
v
v
v
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 12 outputs
c0
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2–98
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1