PLLs and Clock Networks
The connections to the global and regional clocks from the top clock pins
and enhanced PLL outputs are shown in Table 2–20. The connections to
the clocks from the bottom clock pins are shown in Table 2–21.
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 1 of 2)
Top Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK12p
v
v
v
v
v
v
v
v
v
v
v
v
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
v
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL5 outputs
c0
v
v
v
v
v
v
v
v
c1
v
v
2–96
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
