Arria GX Architecture
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 2 of 3)
Left Side Global & Regional Clock
Network Connectivity
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 1 Outputs
c0
c1
c2
c3
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 2 Outputs
c0
c1
c2
c3
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 7 Outputs
c0
c1
c2
c3
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 8 Outputs
Altera Corporation
May 2008
2–93
Arria GX Device Handbook, Volume 1