FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 35. EAB Timing Macroparameters
Symbol
Notes (1), (6)
Parameter
Conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
EAB address access delay
EABAA
EAB asynchronous read cycle time
EABRCCOMB
EABRCREG
EABWP
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EABWCCOMB
EABWCREG
EABDD
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WEsetup time before clock when using input register
EAB WEhold time after clock when using input register
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWESH
EABWDSU
EAB data setup time before falling edge of write pulse when not using input
registers
t
t
t
t
EAB data hold time after falling edge of write pulse when not using input
registers
EABWDH
EABWASU
EABWAH
EABWO
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Altera Corporation
59
ALTERA [ ALTERA CORPORATION ]
