FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 34. EAB Timing Microparameters
Symbol
Note (1)
Parameter
Conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
EAB register clock delay
EABDATA1
EABDATA2
EABWE1
EABWE2
EABCLK
EABCO
EABBYPASS
EABSU
EABH
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
Clock high time
EABCH
EABCL
AA
Clock low time
Address access delay
Write pulse width
WP
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Write enable to data output valid delay
Data-in to data-out valid delay
(5)
(5)
(5)
(5)
WDSU
WDH
WASU
WAH
WO
DD
Data-out delay
EABOUT
58
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