FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
(1)
PRN
D
Q
Dedicated
Clock
CLRN
IOE Register
PRN
Bidirectional
Pin
D
Q
CLRN
(1)
PRN
D
Q
CLRN
Note:
(1) The output enable and input registers are LE registers in the lab adjacent to the
bidirectional pin.
Tables 32 through 36 describe the FLEX 10K device internal timing
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis. Tables 37 through 39 describe FLEX 10K external
timing parameters.
Table 32. LE Timing Microparameters (Part 1 of 2)
Note (1)
Symbol Parameter
Conditions
t
t
t
t
t
t
t
t
t
t
LUT delay for data-in
LUT delay for carry-in
LUT
CLUT
RLUT
PACKED
EN
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
CICO
CGEN
CGENR
CASC
C
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
56
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