FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 36. Interconnect Timing Microparameters
Symbol
Note (1)
Parameter
Conditions
t
t
Routing delay for an LE driving another LE in the same LAB
SAMELAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)
same row
SAMEROW
t
t
Routing delay for an LE driving an IOE in the same column
(7)
SAMECOLUMN
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)
row
DIFFROW
t
t
Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)
TWOROWS
Routing delay for an LE driving a control signal of an IOE via the peripheral (7)
control bus
LEPERIPH
t
t
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
LABCARRY
LABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
t
t
t
t
t
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated clock pin to IOE clock
(7)
(7)
(7)
(7)
(7)
DIN2IOE
DIN2LE
DCLK2IOE
DCLK2LE
DIN2DATA
Delay from dedicated clock pin to LE or EAB clock
Delay from dedicated input or clock to LE or EAB data
Table 37. External Reference Timing Parameters
Note (8)
Symbol Parameter
Conditions
Conditions
t
Register-to-register delay via four LEs, three row interconnects, and four local (9)
interconnects
DRR
Table 38. External Timing Parameters
Symbol
Note (10)
Parameter
t
t
t
Setup time with global clock at IOE register
Hold time with global clock at IOE register
INSU
INH
Clock-to-output delay with global clock at IOE register
OUTCO
60
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