FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 32. LE Timing Microparameters (Part 2 of 2)
Note (1)
Symbol Parameter
Conditions
t
t
t
LE register clock-to-output delay
Combinatorial delay
CO
COMB
SU
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
t
t
t
t
t
LE register hold time for data and enable signals after clock
LE register preset delay
H
PRE
CLR
CH
CL
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
Table 33. IOE Timing Microparameters
Symbol
Note (1)
Parameter
Conditions
t
t
t
t
t
IOE data delay
IOE register control signal delay
IOD
IOC
IOE register clock-to-output delay
IOE combinatorial delay
IOCO
IOCOMB
IOSU
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
t
t
t
t
t
t
t
t
t
t
t
t
IOE register hold time for data and enable signals after clock
IOE register clear time
IOH
IOCLR
OD1
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
= V
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
CCIO
CCIO
CCINT
= low voltage
OD2
OD3
XZ
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
= V
CCINT
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
ZX1
CCIO
CCIO
= low voltage
ZX2
ZX3
INREG
IOFD
INCOMB
IOE input pad and buffer to FastTrack Interconnect delay
Altera Corporation
57
ALTERA [ ALTERA CORPORATION ]
