FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 26. FLEX 10K Device IOE Timing Model
Output Data
Delay
I/O Register
Delays
Output
Delays
tIOD
tIOCO
tIOCOMB
tIOSU
Data-In
tOD1
tOD2
tOD3
tXZ
tIOH
I/O Element
Contol Delay
tIOCLR
tZX1
tZX2
tZX3
Clock Enable
Clear
Clock
tIOC
tINREG
Output Enable
Input Register Delay
I/O Register
Feedback Delay
Data Feedback
into FastTrack
Interconnect
tIOFD
Input Delay
tINCOMB
Figure 27. FLEX 10K Device EAB Timing Model
Input Register
Delays
RAM/ROM
Block Delays
Output Register
Delays
EAB Output
Delay
EAB Data Input
Delays
Data-In
Data-Out
tEABDATA1
tEABDATA2
tEABCO
tEABBYPASS
tEABSU
tEABH
tAA
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABOUT
tDD
Address
tWP
tWDSU
tWDH
tWASU
tWAH
tWO
Write Enable
Input Delays
tEABCH
tEABCL
tEABCH
tEABCL
tEABWE1
tEABWE2
WE
EAB Clock
Delay
Input Register
Clock
tEABCLK
Output Register
Clock
Figures 28 shows the timing model for bidirectional I/O pin timing.
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
