Stratix II and Stratix II GX DDR Memory Support Overview
DQS Delay Chains
The DQS delay chains consist of a set of variable delay elements to allow
the input DQS and DQSn signals to be shifted by the amount given by the
DQS phase-shift circuitry or the logic array. There are four delay elements
in the DQS delay chain; the first delay chain closest to the DQS pin can
either be shifted by the DQS delay settings or by the sum of the DQS delay
setting and the phase-offset setting. The number of delay chains used is
transparent to the users because the altdqsmegafunction automatically
sets it. The DQS delay settings can come from the DQS phase-shift
circuitry on the same side of the device as the target DQS logic block or
from the logic array. When you apply a 0° shift in the altdqs
megafunction, the DQS delay chains are bypassed.
The delay elements in the DQS logic block mimic the delay elements in
the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own 6- or 5-bit settings using the
dqs_delayctrlin[5..0]signals available in the altdqs
megafunction. These settings control 1, 2, 3, or all 4 delay elements in the
DQS delay chains. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps
and the value of the delay steps.
Both the DQS delay settings and the phase-offset settings pass through a
latch before going into the DQS delay chains. The latches are controlled
by the update enable circuitry to allow enough time for any changes in
the DQS delay setting bits to arrive to all the delay elements. This allows
them to be adjusted at the same time. The update enable circuitry enables
the latch to allow enough time for the DQS delay settings to travel from
the DQS phase-shift circuitry to all the DQS logic blocks before the next
change. It uses the input reference clock to generate the update enable
output. The altdqsmegafunction uses this circuit by default. See
Figure 3–12 for an example waveform of the update enable circuitry
output.
The shifted DQS signal then goes to the DQS bus to clock the IOE input
registers of the DQ pins. It can also go into the logic array for
resynchronization purposes. The shifted DQSn signal can only go to the
active-low input register in the DQ IOE and is only used for QDRII SRAM
interfaces.
3–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
