Stratix II and Stratix II GX DDR Memory Support Overview
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]por
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]por PLL 6.
Table 3–10 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 3–10. DQS Delay Buffer Maximum Delay in Fast Timing Model
Frequency
Mode
Maximum Delay Per Delay Buffer
(Fast Timing Model)
Unit
0
0.833
0.416
ns
ns
1, 2, 3
3–26
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
