Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–13. Bidirectional DDR I/O Path in Stratix II and Stratix II GX Devices
Note (1)
DFF
OE
(2)
D
Q
OR2
(3)
OE Register A
OE
1
0
(4)
DFF
D
Q
OE Register B
(5)
OE
DFF
datain_l
D
Q
I/O Pin (7)
(6)
TRI
0
1
Output Register A
O
DFF
Logic Array
datain_h
D
Q
Output Register B
O
outclock
combout
DFF
dataout_h
Q
D
Input Register A
I
Latch
Q
TCHLA
DFF
dataout_l
neg_reg_out
D
Q
D
ENA
Input Register B
(8)
Latch C
I
I
inclock
Notes to Figure 3–13:
(1) All control signals can be inverted at the IOE. The signal names used here match with Quartus II software naming
convention.
(2) The OEsignal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the AOE register during compilation.
(3) The AOE register generates the enable signal for general-purpose DDR I/O applications.
(4) This select line is to choose whether the OEsignal should be delayed by half-a-clock cycle.
(5) The BOE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.
(6) The tristate enable is by default active low. You can, however, design it to be active high. The combinational control
path for the tristate is not shown in this diagram.
(7) You can also have combinational output to the I/O pin; this path is not shown in the diagram.
(8) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–32
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
