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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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External Memory Interfaces in Stratix II and Stratix II GX Devices  
Figure 3–10. Simplified Diagram of the DQS Phase-Shift Circuitry  
Note (1)  
addnsub  
Phase offset settings  
from the logic array  
DLL  
6
Input reference  
clock (2)  
Phase  
Offset  
Control  
upndn  
Phase offset  
settings (3)  
Phase  
Comparator  
Up/Down  
Counter  
6
clock enable  
6
Delay Chains  
DQS delay  
settings (4)  
6
6
Notes to Figure 3–10:  
(1) All features of the DQS phase-shift circuitry are accessible from the altdqs megafunction in the Quartus II software.  
You should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory  
interface.  
(2) The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from  
CLK[15..12]por PLL 5. The input reference clock for the DQS phase-shift circuitry on the bottom side of the  
device can come from CLK[7..4]por PLL 6.  
(3) Phase offset settings can only go to the DQS logic blocks.  
(4) DQS delay settings can go to the logic array and/or to the DQS logic block.  
The input reference clock goes into the DLL to a chain of up to 16 delay  
elements. The phase comparator compares the signal coming out of the  
end of the delay element chain to the input reference clock. The phase  
comparator then issues the upndnsignal to the up/down counter. This  
signal increments or decrements a six-bit delay setting (DQS delay  
settings) that will increase or decrease the delay through the delay  
element chain to bring the input reference clock and the signals coming  
out of the delay element chain in phase.  
The DQS delay settings contain the control bits to shift the signal on the  
input DQS pin by the amount set in the altdqsmegafunction. For the 0°  
shift, both the DLL and the DQS logic block are bypassed. Since Stratix II  
and Stratix II GX DQS and DQ pins are designed such that the pin to IOE  
delays are matched, the skew between the DQ and DQS pin at the DQ IOE  
registers is negligible when the 0° shift is implemented. You can feed the  
DQS delay settings to the DQS logic block and the logic array.  
Altera Corporation  
January 2008  
3–27  
Stratix II Device Handbook, Volume 2  
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