External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–14. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note (1)
System clock
(outclock for DQS)
OE for DQS
(from logic array)
Delay
by Half
a Clock
Cycle
90˚
DQS
Preamble
Postamble
Write Clock
(outclock for DQ,
−90° phase shifted
from System Clock)
datain_h
(from logic array)
D0
D1
D2
D3
datain_l
(from logic array)
OE for DQ
(from logic array)
D0
D1
D2
D3
DQ
Note to Figure 3–14:
(1) The waveform reflects the software simulation result. The OEsignal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the AOE
register D input.
Figures 3–15 and 3–16 summarize the IOE registers used for the DQ and
DQS signals.
Altera Corporation
January 2008
3–33
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
