Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–15. DQ Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
(2)
D
Q
OE
OE Register A
OE
DFF
D
Q
datain_l
TRI
0
1
DQ Pin
Output Register A
O
DFF
Logic Array
D
Q
datain_h
Output Register B
O
outclock (3)
DFF
D
Q
dataout_h
Input Register A
I
Latch
TCLHA
DFF
neg_reg_out
Q
D
Q
D
(4)
ENA
dataout_l
Input Register B (6)
Latch C
I
I
inclock (from DQS bus)
(5)
Notes to Figure 3–15:
(1) You can use the altdqmegafunction to generate the DQ signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
(2) The OEsignal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OEregister AOE during compilation.
(3) The outclocksignal for DDR, DDR2 SDRAM, and QDRII SRAM interfaces has a 90° phase-shift relationship with
the system clock. For 300-MHz RLDRAM II interfaces with EP2S60F1020C3, Altera recommends a 75° phase-shift
relationship.
(4) The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SRAM interfaces.
(5) The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the
altdqmegafunction to generate the DQ signals. Connect this port to the comboutport in the altdqs
megafunction.
(6) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–34
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
