Stratix II and Stratix II GX DDR Memory Support Overview
Phase Offset Control
The DQS phase-shift circuitry also contains a phase offset control module
that can add or subtract a phase offset amount from the DQS delay setting
(phase offset settings from the logic array in Figure 3–10). You should use
the phase offset control module for making small shifts to the input signal
and use the DQS phase-shift circuitry for larger signal shifts. For example,
if you need the input signal to be shifted by 75°, you can set the altdqs
megafunction to generate a 72° phase shift with a phase offset of +3°.
You can either use a static phase offset or a dynamic phase offset to
implement the additional phase shift. The available additional phase shift
is implemented in 2s-complement between settings –64 to +63 for
frequency mode 0, and between settings –32 to +31 for frequency modes
1, 2, and 3. However, the DQS delay settings are at the maximum at
setting 64 for frequency mode 0, and at the maximum at setting 32 for
frequency modes 1, 2, and 3. Therefore, the actual physical offset setting
range will be 64 or 32 subtracted by the DQS delay settings from the DLL.
For example, if the DLL determines that to achieve 30° you will need a
DQS delay setting of 28, you can subtract up to 28 phase offset settings
and you can add up to 36 phase offset settings to achieve the optimal
delay.
1
Each phase offset setting translates to a certain delay, as
specified in the DC & Switching Characteristics of Stratix III
Devices chapter in volume 2 of the Stratix III Device Handbook.
When using the static phase offset, you can specify the phase offset
amount in the altdqsmegafunction as a positive number for addition or
a negative number for subtraction. You can also have a dynamic phase
offset that is always added to, subtracted from, or both added to and
subtracted from the DLL phase shift. When you always add or subtract,
you can dynamically input the phase offset amount into the
dll_offset[5..0]port. When you want to both add and subtract
dynamically, you control the addnsubsignal in addition to the
dll_offset[5..0]signals.
DQS Logic Block
Each DQS and DQSn pin is connected to a separate DQS logic block (see
Figure 3–11). The logic block contains DQS delay chains and postamble
circuitry.
3–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
