Stratix II and Stratix II GX DDR Memory Support Overview
The phase-shift circuitry is only used during read transactions where the
DQS and DQSn pins are acting as input clocks or strobes. The phase-shift
circuitry can shift the incoming DQS signal by 0°, 22.5°, 30°, 36°, 45°, 60°,
67.5°, 72°, 90°, 108°, 120°, or 144°. The shifted DQS signal is then used as
clocks at the DQ IOE input registers.
Figure 3–3 shows an example where the DQS signal is shifted by 90°. The
DQS signals goes through the 90° shift delay set by the DQS phase-shift
circuitry and the DQS logic block and some routing delay from the DQS
pin to the DQ IOE registers. The DQ signals only goes through routing
delay from the DQ pin to the DQ IOE registers and maintains the 90°
relationship between the DQS and DQ signals at the DQ IOE registers
since the software will automatically set delay chains to match the routing
delay between the pins and the IOE registers for the DQ and DQS input
paths.
All 18 DQS and DQSn pins on either the top or bottom of the device can
have their input signal phase shifted by a different degree amount but all
must be referenced at one particular frequency. For example you can have
a 90° phase shift on DQS0Tand have a 60° phase shift on DQS1Tboth
referenced from a 200-MHz clock. Not all phase-shift combinations are
supported, however. The phase shifts on the same side of the device must
all be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), or a
multiple of 36° (up to 144°).
In order to generate the correct phase shift with the DLL used, you must
provide a clock signal of the same frequency as the DQS signal to the DQS
phase-shift circuitry. Any of the CLK[15..12]pclock pins can feed the
phase circuitry on the top of the device (I/O banks 3 and 4) or any of the
CLK[7..4]pclock pins can feed the phase circuitry on the bottom of the
device (I/O banks 7 and 8). Stratix II and Stratix II GX devices can also
use PLLs 5 or 6 as the reference clock to the DQS phase-shift circuitry on
the top or bottom of the device, respectively. PLL 5 is connected to the
DQS phase-shift circuitry on the top side of the device and PLL 6 is
connected to the DQS phase-shift circuitry on the bottom side of the
device. Both the top and bottom phase-shift circuits need unique clock
pins or PLL clock outputs for the reference clock.
1
When you have a PLL dedicated only to generate the DLL input
reference clock, you must set the PLL mode to “No
Compensation” or the Quartus® II software will change it
automatically. Because there are no other PLL outputs used, the
PLL doesn’t need to compensate for any clock paths.
3–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
