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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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External Memory Interfaces in Stratix II and Stratix II GX Devices  
DLL  
The DQS phase-shift circuitry uses a delay-locked loop (DLL) to  
dynamically measure the clock period needed by the DQS/DQSn pin (see  
Figure 3–10). The DQS phase-shift circuitry then uses the clock period to  
generate the correct phase shift. The DLL in the Stratix II or Stratix II GX  
DQS phase-shift circuitry can operate between 100 and 400 MHz. The  
phase-shift circuitry needs a maximum of 256 clock cycles to calculate the  
correct input clock period. Data sent during these clock cycles may not be  
properly captured.  
1
Although the DLL can run up to 400 MHz, other factors may  
prevent you from interfacing with a 400-MHz external memory  
device.  
1
You can still use the DQS phase-shift circuitry for any memory  
interfaces that are less than 100 MHz. The DQS signal will be  
shifted by 2.5 ns and you can add more shift by using the phase  
offset module. Even if the DQS signal is not shifted exactly to the  
middle of the DQ valid window, the IOE should still be able to  
capture the data in this low frequency application.  
There are four different frequency modes for the Stratix II or Stratix II GX  
DLL. Each frequency mode provides different phase shift, as shown in  
Table 3–9.  
Table 3–9. Stratix II and Stratix II GS DLL Frequency Modes  
Frequency  
Mode  
Available  
Phase Shift Delay Chains  
Number of  
Frequency Range (MHz)  
0
1
2
3
100–175  
30, 60, 90,  
120  
12  
16  
12  
10  
150–230  
200–310  
22.5, 45,  
67.5, 90  
30, 60, 90,  
120  
240–400 (C3 speed grade)  
240–350 (C4 and C5 speed grades)  
36, 72, 108,  
144  
In frequency mode 0, Stratix II devices use a 6-bit setting to implement the  
phase-shift delay. In frequency modes 1, 2, and 3, Stratix II devices only  
use a 5-bit setting to implement the phase-shift delay.  
The DLL can be reset from either the logic array or a user I/O pin. This  
signal is not shown in Figure 3–10. Each time the DLL is reset, you must  
wait for 256 clock cycles before you can capture the data properly.  
Altera Corporation  
January 2008  
3–25  
Stratix II Device Handbook, Volume 2  
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