PLLs in Stratix II and Stratix II GX Devices
Table 1–20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices EP2S60 to EP2S180 Devices
Enhanced
Enhanced
PLLs
Input Pin
Fast PLLs
Fast PLLs
PLLs
1
2
3
4
5
6
7
8
9
10
11 12
FPLL10CLK (2)
v
Notes to Table 1–20:
(1) Clock connection is available. For more information about the maximum frequency, contact Altera Applications.
(2) This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
Table 1–21. Stratix II GX Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices
Fast PLLs
EP2SGX60 to EP2SGX130 Devices
Enhanced
PLLs
Enhanced
Input Pin
Fast PLLs
PLLs
1
2
3 (1) 4 (1)
5
6
7
8
9 (1) 10 (1) 11
12
CLK0
v
v
v
v
v
v
v
v
v(2) v(2)
v(2) v(2)
v(2) v(2)
v(2) v(2)
CLK1 (2)
CLK2
CLK3 (2)
CLK4
v
v
v
v
v
v
v
v
CLK5
CLK6
CLK7
CLK8 (4)
CLK9 (3), (4)
CLK10 (4)
CLK11 (3), (4)
CLK12
v
v
v
v
v
v
v
v
v
CLK13
CLK14
CLK15
PLL5_FB
PLL6_FB
PLL11_FB
v
v
Altera Corporation
July 2009
1–71
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
