Clocking
Table 1–21. Stratix II GX Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices
Fast PLLs
EP2SGX60 to EP2SGX130 Devices
Enhanced
PLLs
Enhanced
PLLs
Input Pin
Fast PLLs
8
1
2
3 (1) 4 (1)
5
6
7
9 (1) 10 (1) 11
12
PLL12_FB
v
v
PLL_ENA
v
v
v
v
v
v
v
v
v
FPLL7CLK (3)
FPLL8CLK (3)
FPLL9CLK (3)
FPLL10CLK (3)
Notes to Table 1–21:
(1) PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices.
(2) Clock connection is available. For more information about the maximum frequency, contact Altera Applications.
(3) This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
(4) Input pins CLK[11..8]are not available in Stratix II GX devices.
CLK(n) Pin Connectivity to Global Clock Networks
In Stratix II and Stratix II GX devices, the clk(n)pins can also feed the
global clock network. Table 1–22 shows the clk(n)pin connectivity to
global clock networks.
Table 1–22. CLK(n) Pin Connectivity to Global Clock Network
Clock
Resource
CLK(n) pin
4
5
6
7
12
13
14
15
GCLK4
GCLK5
GCLK6
GCLK7
GCLK12
GCLK13
GCLK14
GCLK15
v
v
v
v
v
v
v
v
1–72
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
ALTERA [ ALTERA CORPORATION ]
