Clocking
Table 1–19 summarizes the connectivity between the clock pins and the
regional clock networks. Here, each clock pin can drive two regional clock
networks, facilitating stitching of the clock networks to support the
ability to drive two quadrants with the same clock or signal.
Table 1–19. Clock Input Pin Connectivity to Regional Clock Networks (Part 1 of 2)
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
(1)
RCLK17
RCLK18
RCLK19
RCLK20
RCLK21
RCLK22
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
1–68
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
