PLLs in Stratix II and Stratix II GX Devices
Delay Compensation for Fast PLLs
Each center fast PLL can be fed by any one of four possible input clock
pins. Among the four clock input signals, only two are fully
compensated, i.e., the clock delay to the fast PLL matches the delay in the
data input path when used in the LVDS receiver mode. The two clock
inputs that match the data input path are located right next to the fast
PLL. The two clock inputs that do not match the data input path are
located next to the neighboring fast PLL. Figure 1–46 shows the above
description for the left-side center fast PLL pair. If the PLL is used in
non-LVDS modes, then any of the four dedicated clock inputs can be used
and are compensated.
Fast PLL 1 and PLL 2 can choose among CLK[3..0]as the clock input
source. However, for fast PLL 1, only CLK0and CLK1have their delay
matched to the data input path delay when used in the LVDS receiver
mode operation. The delay from CLK2or CLK3to fast PLL 1 does not
match the data input delay. For fast PLL 2, only CLK2and CLK3have their
delay matched to the data input path delay in LVDS receiver mode
operation. The delay from CLK0or CLK1to fast PLL 2 does not match the
data input delay. The same arrangement applies to the right side center
fast PLL pair. For corner fast PLLs, only the corner FPLLCLKpins are fully
compensated. For LVDS receiver operation, it is recommended to use the
delay compensated clock pins only.
Figure 1–46. Delay Compensated Clock Input Pins for Center Fast PLL Pair
CLK0
CLK1
Fast PLL 1
Fast PLL 2
CLK2
CLK3
Altera Corporation
July 2009
1–75
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
