PLLs in Stratix II and Stratix II GX Devices
Table 1–18 shows the connection of the clock pins to the global clock
resources. The reason for the higher level of connectivity is to support
user controllable global clock multiplexing.
Table 1–18. Clock Input Pin Connectivity to Global Clock Networks
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
(1) (1)
GCLK9
v
v
(1) (1)
GCLK10
GCLK11
v
v
(1) (1)
v
v
(1) (1)
GCLK12
GCLK13
GCLK14
GCLK15
v
v
v
v
v
v
v
v
Note to Table 1–18:
(1) Clock pins 8, 9, 10, and 11 are not available in Stratix II GX devices. Therefore, these connections do not exist in
Stratix II GX devices.
Altera Corporation
July 2009
1–67
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
