PLLs in Stratix II and Stratix II GX Devices
Table 1–19. Clock Input Pin Connectivity to Regional Clock Networks (Part 2 of 2)
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
RCLK23
v
(1)
RCLK24
RCLK25
RCLK26
RCLK27
RCLK28
RCLK29
RCLK30
RCLK31
v
v
v
v
v
v
v
v
Note to Table 1–19:
(1) Clock pins 8, 9, 10, and 11 are not available in Stratix II GX devices. Therefore, these connections do not exist in
Stratix II GX devices.
Clock Input Connections
Four CLKpins drive each enhanced PLL. You can use any of the pins for
clock switchover inputs into the PLL. The CLKpins are the primary clock
source for clock switchover, which is controlled in the Quartus II
software. Enhanced PLLs 5, 6, 11, and 12 also have feedback input pins,
as shown in Table 1–20.
Input clocks for fast PLLs 1, 2, 3, and 4 come from CLKpins. A multiplexer
chooses one of two possible CLKpins to drive each PLL. This multiplexer
is not a clock switchover multiplexer and is only used for clock input
connectivity.
Either an FPLLCLKinput pin or a CLKpin can drive the fast PLLs in the
corners (7, 8, 9, and 10) when used for general-purpose applications. CLK
pins cannot drive these fast PLLs in high-speed differential I/O mode.
Altera Corporation
July 2009
1–69
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
