Clocking
Tables 1–20 and 1–21 show which PLLs are available in each Stratix II and
Stratix II GX device, respectively, and which input clock pin drives which
PLLs.
Table 1–20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices EP2S60 to EP2S180 Devices
Enhanced
PLLs
Enhanced
PLLs
Input Pin
Fast PLLs
Fast PLLs
1
2
3
4
5
6
7
8
9
10
11
12
CLK0
v
v
v
v
v
v
v
v
v (1) v (1)
v (1) v (1)
v (1) v (1)
v (1) v (1)
CLK1 (2)
CLK2
CLK3 (2)
CLK4
v
v
v
v
v
v
v
v
CLK5
CLK6
CLK7
CLK8
v
v
v
v
v
v
v
v
v (1) v (1)
v (1) v (1)
v (1) v (1)
v (1) v (1)
CLK9 (2)
CLK10
CLK11 (2)
CLK12
v
v
v
v
v
v
v
v
v
CLK13
CLK14
CLK15
PLL5_FB
PLL6_FB
PLL11_FB
PLL12_FB
PLL_ENA
FPLL7CLK (2)
FPLL8CLK (2)
FPLL9CLK (2)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1–70
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
