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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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PLLs in Stratix II and Stratix II GX Devices  
Clock Source Control For Enhanced PLLs  
The clock input multiplexer for enhanced PLLs is shown in Figure 1–43.  
This block allows selection of the PLL clock reference from several  
different sources. The clock source to an enhanced PLL can come from  
any one of four clock input pins CLK[3..0], or from a logic-array clock,  
provided the logic array clock is driven by an output from another PLL,  
a pin-driven dedicated global or regional clock, or through a clock control  
block, provided the clock control block is fed by an output from another  
PLL or a pin-driven dedicated global or regional clock. An internally  
generated global signal cannot drive the PLL. The clock input pin  
connections to the respective enhanced PLLs are shown in Table 1–20  
above. The multiplexer select lines are set in the configuration file only.  
Once programmed, this block cannot be changed without loading a new  
configuration file. The Quartus II software automatically sets the  
multiplexer select signals depending on the clock sources that a user  
selects in the design.  
Figure 1–43. Enhanced PLL Clock Input Multiplex Logic  
(1)  
4
clk[3..0]  
inclk0  
core_inclk  
To the Clock  
Switchover Block  
(1)  
inclk1  
4
Note to Figure 1–43:  
(1) The input clock multiplexing is controlled through a configuration file only and  
cannot be dynamically controlled in user mode.  
Clock Source Control for Fast PLLs  
Each center fast PLL has five clock input sources, four from clock input  
pins, and one from a logic array signal, provided the logic array signal is  
driven by an output from another PLL, a pin-driven dedicated global or  
regional clock, or through a clock control block, provided the clock  
control block is fed by an output from another PLL or a pin-driven  
dedicated global or regional clock. An internally generated global signal  
cannot drive the PLL. When using clock input pins as the clock source,  
you can perform manual clock switchover among the input clock sources.  
Altera Corporation  
July 2009  
1–73  
Stratix II Device Handbook, Volume 2  
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