PLLs in Stratix II and Stratix II GX Devices
Figure 1–41. Hierarchical Clock Networks Per Quadrant
Clocks Available
Column I/O Cell
IO_CLK[7..0]
to a Quadrant
or Half-Quadrant
Global Clock Network [15..0]
Regional Clock Network [7..0]
Clock [23..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
Stratix II and Stratix II GX clock networks provide three different clocking
regions:
■
Entire device clock region
Quadrant clock region
Dual-regional clock region
■
■
These clock network options provide more flexibility for routing signals
that have high fan-out to improve the interface timing. By having various
sized clock regions, it is possible to prioritize the number of registers the
network can reach versus the total delay of the network.
In the first clock scheme, a source (not necessarily a clock signal) drives a
global clock network that can be routed through the entire device. This
has the maximum delay for a low skew high fan-out signal but allows the
signal to reach every block within the device. This is a good option for
routing global resets or clear signals.
In the second clock scheme, a source drives a single-quadrant region. This
represents the fastest, low-skew, high-fan-out signal-routing resource
within a quadrant. The limitation to this resource is that it only covers a
single quadrant.
In the third clock scheme, a single source (clock pin or PLL output) can
generate a dual-regional clock by driving two regional clock network
lines (one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low-skew clock. The routing of this signal
on an entire side has approximately the same speed as in a quadrant clock
region. The internal logic-array routing that can drive a regional clock
also supports this feature. This means internal logic can drive a
Altera Corporation
July 2009
1–65
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
