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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-87  
Programmable IOE Delay  
e Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design afer you complete  
place-and-route.  
Related Information  
Arria V I/O Timing Spreadsheet  
Provides the Arria V Excel-based I/O timing spreadsheet.  
Programmable IOE Delay  
Table 1-76: I/O element (IOE) Programmable Delay for Arria V Devices  
Fast Model  
Slow Model  
–C6  
Parameter(112  
Available  
Settings  
Minimum  
Unit  
)
Offset(113)  
Industrial  
Commercial  
0.517  
–C4  
–C5  
–I3  
–I5  
D1  
D3  
D4  
D5  
32  
8
0
0
0
0
0.508  
1.763  
0.508  
0.508  
0.870  
2.999  
0.869  
0.870  
1.063  
3.496  
1.063  
1.063  
1.063  
0.872  
1.057  
ns  
ns  
ns  
ns  
1.795  
3.571  
3.031  
1.063  
0.872  
3.643  
1.057  
1.057  
32  
32  
0.518  
1.063  
0.517  
1.063  
Programmable Output Buffer Delay  
Table 1-77: Programmable Output Buffer Delay for Arria V Devices  
is table lists the delay chain settings that control the rising and falling edge delays of the output buffer.  
You can set the programmable output buffer delay in the Quartus Prime sofꢂare by setting the Output Buffer Delay Control assignment to either  
positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.  
(112)  
(113)  
You can set this value in the Quartus Prime sofꢂare by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.  
Minimum offset does not include the intrinsic delay.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 
 
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