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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-86  
Remote System Upgrades  
Remote System Upgrades  
Table 1-74: Remote System Upgrade Circuitry Timing Specifications for Arria V Devices  
Parameter  
Minimum  
250  
Unit  
ns  
(110)  
(111)  
tRU_nCONFIG  
tRU_nRSTIMER  
250  
ns  
Related Information  
Remote System Upgrade State Machine  
Provides more information about configuration reset (RU_CONFIG) signal.  
User Watchdog Timer  
Provides more information about reset_timer (RU_nRSTIMER) signal.  
User Watchdog Internal Oscillator Frequency Specifications  
Table 1-75: User Watchdog Internal Oscillator Frequency Specifications for Arria V Devices  
Parameter  
Minimum  
Typical  
Maximum  
Unit  
User watchdog internal oscillator frequency  
5.3  
7.9  
12.5  
MHz  
I/O Timing  
Altera offers two ways to determine I/O timing—the Excel-based I/O timing and the Quartus Prime Timing Analyzer.  
Excel-based I/O timing provides pin timing performance for each device density and speed grade. e data is typically used prior to designing the  
FPGA to get an estimate of the timing budget as part of the link timing analysis.  
(110)  
(111)  
is is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.  
is is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 
 
 
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